An Auto-tuning Jit Compiler for Accelerating Multiple Stencil Computations

We present a JIT compiler with auto-tuning capabilities fusing multiple stencil computations. Data arrays for scientific computing of image processing often exceed cache-memory size. To take advantage of spatial and temporal locality, a common method is to partition the images into tiling blocks for multicore architectures. In realistic scenarios, the multiple image algorithms, most of which are stencil computations, should be processed consecutively. We fuse those stencil codes on the tiled edge-aware image blocks for efficient parallel computing. In this work, multiple kernels are concatenated and blocking according to the images’ dimension and the cache memory size of current hardware. To avoid high load communication, a sufficient number of halo layers are added. One auto-tuning strategy can keep an optimal balance between block size and the number of halo layers. Compared to hand-optimized naïve schemes, experiment using our task parallel model achieves at least 50% improvement of system performance on three CPUs workstations.